[Buildroot] [PATCH v7 01/10] package/binutils-bare-metal: new package

Neal Frager neal.frager at amd.com
Mon Nov 20 14:08:19 UTC 2023


This patch adds a new package for building binutils for a bare-metal toolchain.
The cpu architecture is defined by a toolchain-bare-metal virtual package.
While any cpu architecture could be used, the default configuration will be a
Xilinx microblaze little endian architecture, so that buildroot will be able
to build the microblaze firmware applications for zynqmp and versal.

In order to build the zynqmp pmufw and versal plm applications without error,
binutils version 2.41 or higher is required with the following patches.  All
six of these patches have been applied upstream.

0003-opcodes-microblaze-Add-wdc-instructions.patch:
https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=a4045fdf2e859a23b7817f6dd5b18a1f6d22fc49

0004-opcodes-microblaze-Add-suspend-instructions.patch:
https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=6487710babec2e7dcae997f79e03b9ec7d78e1c3

0005-opcodes-microblaze-Add-address-entension-instructions.patch:
https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=b90eb3e5b25c22ec6ee476e500aa902f77b43349

0006-opcodes-microblaze-Add-new-bit-field-instructions.patch:
https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=bb0d05ff74fda6b8f3f83712ebba3ea36bff1426

0007-bfd-microblaze-Add-32_NONE-reloc-type.patch:
https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=d605374748fef3d3b1dea713e78bbef9c8b0fb65

0008-opcodes-microblaze-Fix-bit-masking-bug.patch:
https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=2d1777b530d7832db5d8d7017378354c28816554

Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza at amd.com>
Signed-off-by: Neal Frager <neal.frager at amd.com>
---
V1->V2:
 - removed default enable to be replaced with toolchain select config
V2->V3:
 - no changes
V3->V4:
 - split tar instruction into multiple lines
 - replaced unnecessary =? with = for assignments
 - changed xlnx-rel-v2023.1.tar.gz hash to sha256
 - improved menuconfig help comment
V4->V5:
 - moved to upstream version 2.41 with needed patches
 - reduced all lines to <80 chars
V5->V6:
 - migrated to toolchain-bare-metal-buildroot
V6->V7:
 - removed Config.in and hard-coded version
---
 DEVELOPERS                                    |   4 +
 package/binutils-bare-metal/2.41              |   1 +
 .../binutils-bare-metal.hash                  |   1 +
 .../binutils-bare-metal.mk                    |  35 +++
 ...odes-microblaze-Add-wdc-instructions.patch |  83 ++++++
 ...-microblaze-Add-suspend-instructions.patch |  24 ++
 ...e-Add-address-entension-instructions.patch |  78 ++++++
 ...blaze-Add-new-bit-field-instructions.patch | 265 ++++++++++++++++++
 ...fd-microblaze-Add-32_NONE-reloc-type.patch | 180 ++++++++++++
 ...codes-microblaze-Fix-bit-masking-bug.patch |  80 ++++++
 10 files changed, 751 insertions(+)
 create mode 120000 package/binutils-bare-metal/2.41
 create mode 120000 package/binutils-bare-metal/binutils-bare-metal.hash
 create mode 100644 package/binutils-bare-metal/binutils-bare-metal.mk
 create mode 100644 package/binutils/2.41/0003-opcodes-microblaze-Add-wdc-instructions.patch
 create mode 100644 package/binutils/2.41/0004-opcodes-microblaze-Add-suspend-instructions.patch
 create mode 100644 package/binutils/2.41/0005-opcodes-microblaze-Add-address-entension-instructions.patch
 create mode 100644 package/binutils/2.41/0006-opcodes-microblaze-Add-new-bit-field-instructions.patch
 create mode 100644 package/binutils/2.41/0007-bfd-microblaze-Add-32_NONE-reloc-type.patch
 create mode 100644 package/binutils/2.41/0008-opcodes-microblaze-Fix-bit-masking-bug.patch

diff --git a/DEVELOPERS b/DEVELOPERS
index 1f26e9bc81..d06b280500 100644
--- a/DEVELOPERS
+++ b/DEVELOPERS
@@ -1381,6 +1381,9 @@ F:	package/mrp/
 N:	Ian Haylock <haylocki at yahoo.co.uk>
 F:	package/python-rpi-gpio/
 
+N:	Ibai Erkiaga <ibai.erkiaga-elorza at amd.com>
+F:	package/binutils-bare-metal/
+
 N:	Ignacy Gawędzki <ignacy.gawedzki at green-communications.fr>
 F:	package/angularjs/
 
@@ -2214,6 +2217,7 @@ F:	configs/zynq_zc706_defconfig
 F:	configs/zynqmp_kria_kv260_defconfig
 F:	configs/zynqmp_zcu102_defconfig
 F:	configs/zynqmp_zcu106_defconfig
+F:	package/binutils-bare-metal/
 F:	package/bootgen/
 F:	package/versal-firmware/
 
diff --git a/package/binutils-bare-metal/2.41 b/package/binutils-bare-metal/2.41
new file mode 120000
index 0000000000..80b037b8be
--- /dev/null
+++ b/package/binutils-bare-metal/2.41
@@ -0,0 +1 @@
+../binutils/2.41
\ No newline at end of file
diff --git a/package/binutils-bare-metal/binutils-bare-metal.hash b/package/binutils-bare-metal/binutils-bare-metal.hash
new file mode 120000
index 0000000000..e0655d3af3
--- /dev/null
+++ b/package/binutils-bare-metal/binutils-bare-metal.hash
@@ -0,0 +1 @@
+../binutils/binutils.hash
\ No newline at end of file
diff --git a/package/binutils-bare-metal/binutils-bare-metal.mk b/package/binutils-bare-metal/binutils-bare-metal.mk
new file mode 100644
index 0000000000..c598dcdaed
--- /dev/null
+++ b/package/binutils-bare-metal/binutils-bare-metal.mk
@@ -0,0 +1,35 @@
+################################################################################
+#
+# binutils-bare-metal
+#
+################################################################################
+
+HOST_BINUTILS_BARE_METAL_VERSION = 2.41
+
+HOST_BINUTILS_BARE_METAL_SITE = $(BR2_GNU_MIRROR)/binutils
+HOST_BINUTILS_BARE_METAL_SOURCE = \
+	binutils-$(HOST_BINUTILS_BARE_METAL_VERSION).tar.xz
+
+HOST_BINUTILS_BARE_METAL_LICENSE = GPL-3.0+, libiberty LGPL-2.1+
+HOST_BINUTILS_BARE_METAL_LICENSE_FILES = COPYING3 COPYING.LIB
+HOST_BINUTILS_BARE_METAL_CPE_ID_VENDOR = gnu
+
+HOST_BINUTILS_BARE_METAL_DEPENDENCIES = host-zlib
+
+# Don't build documentation. It takes up extra space / build time,
+# and sometimes needs specific makeinfo versions to work
+HOST_BINUTILS_BARE_METAL_CONF_ENV += MAKEINFO=true
+HOST_BINUTILS_BARE_METAL_MAKE_OPTS += MAKEINFO=true
+HOST_BINUTILS_BARE_METAL_INSTALL_OPTS += MAKEINFO=true install
+
+HOST_BINUTILS_BARE_METAL_CONF_OPTS = \
+	--target=$(BR2_TOOLCHAIN_BARE_METAL_BUILDROOT_ARCH) \
+	--disable-gprof \
+	--disable-shared \
+	--enable-lto \
+	--enable-static \
+	--disable-initfini-array \
+	--disable-multilib \
+	--disable-werror
+
+$(eval $(host-autotools-package))
diff --git a/package/binutils/2.41/0003-opcodes-microblaze-Add-wdc-instructions.patch b/package/binutils/2.41/0003-opcodes-microblaze-Add-wdc-instructions.patch
new file mode 100644
index 0000000000..db102aacaf
--- /dev/null
+++ b/package/binutils/2.41/0003-opcodes-microblaze-Add-wdc-instructions.patch
@@ -0,0 +1,83 @@
+From a4045fdf2e859a23b7817f6dd5b18a1f6d22fc49 Mon Sep 17 00:00:00 2001
+From: Neal Frager <neal.frager at amd.com>
+Date: Wed, 27 Sep 2023 14:47:01 +0100
+Subject: [PATCH] opcodes: microblaze: Add wdc.ext.clear and wdc.ext.flush
+ insns
+
+---
+ opcodes/microblaze-opc.h  | 31 +++++++++++++++++--------------
+ opcodes/microblaze-opcm.h |  4 ++--
+ 2 files changed, 19 insertions(+), 16 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 94048e67551..7c70c80a27b 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -74,24 +74,25 @@
+ #define IMMVAL_MASK_MTS 0x4000
+ #define IMMVAL_MASK_MFS 0x0000
+ 
+-#define OPCODE_MASK_H   0xFC000000  /* High 6 bits only.  */
+-#define OPCODE_MASK_H1  0xFFE00000  /* High 11 bits.  */
+-#define OPCODE_MASK_H2  0xFC1F0000  /* High 6 and bits 20-16.  */
+-#define OPCODE_MASK_H12 0xFFFF0000  /* High 16.  */
+-#define OPCODE_MASK_H4  0xFC0007FF  /* High 6 and low 11 bits.  */
+-#define OPCODE_MASK_H13S 0xFFE0E7F0 /* High 11 16:18 21:27 bits, 19:20 bits
++#define OPCODE_MASK_H     0xFC000000 /* High 6 bits only.  */
++#define OPCODE_MASK_H1    0xFFE00000 /* High 11 bits.  */
++#define OPCODE_MASK_H2    0xFC1F0000 /* High 6 and bits 20-16.  */
++#define OPCODE_MASK_H12   0xFFFF0000 /* High 16.  */
++#define OPCODE_MASK_H4    0xFC0007FF /* High 6 and low 11 bits.  */
++#define OPCODE_MASK_H13S  0xFFE0E7F0 /* High 11 16:18 21:27 bits, 19:20 bits
+                                        and last nibble of last byte for spr.  */
+-#define OPCODE_MASK_H23S 0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last
++#define OPCODE_MASK_H23S  0xFC1FC000 /* High 6, 20-16 and 15:1 bits and last
+ 				       nibble of last byte for spr.  */
+-#define OPCODE_MASK_H34 0xFC00FFFF  /* High 6 and low 16 bits.  */
+-#define OPCODE_MASK_H14 0xFFE007FF  /* High 11 and low 11 bits.  */
+-#define OPCODE_MASK_H24 0xFC1F07FF  /* High 6, bits 20-16 and low 11 bits.  */
++#define OPCODE_MASK_H34   0xFC00FFFF /* High 6 and low 16 bits.  */
++#define OPCODE_MASK_H14   0xFFE007FF /* High 11 and low 11 bits.  */
++#define OPCODE_MASK_H24   0xFC1F07FF /* High 6, bits 20-16 and low 11 bits.  */
+ #define OPCODE_MASK_H124  0xFFFF07FF /* High 16, and low 11 bits.  */
+ #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits.  */
+-#define OPCODE_MASK_H3  0xFC000600  /* High 6 bits and bits 21, 22.  */
+-#define OPCODE_MASK_H32 0xFC00FC00  /* High 6 bits and bit 16-21.  */
+-#define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits.  */
+-#define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26.  */
++#define OPCODE_MASK_H3    0xFC000600 /* High 6 bits and bits 21, 22.  */
++#define OPCODE_MASK_H32   0xFC00FC00 /* High 6 bits and bit 16-21.  */
++#define OPCODE_MASK_H34B  0xFC0000FF /* High 6 bits and low 8 bits.  */
++#define OPCODE_MASK_H35B  0xFC0004FF /* High 6 bits and low 9 bits.  */
++#define OPCODE_MASK_H34C  0xFC0007E0 /* High 6 bits and bits 21-26.  */
+ 
+ /* New Mask for msrset, msrclr insns.  */
+ #define OPCODE_MASK_H23N  0xFC1F8000 /* High 6 and bits 11 - 16.  */
+@@ -174,7 +175,9 @@ const struct op_code_struct
+   {"wic",   INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000068, OPCODE_MASK_H34B, wic, special_inst },
+   {"wdc",   INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000064, OPCODE_MASK_H34B, wdc, special_inst },
+   {"wdc.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000066, OPCODE_MASK_H34B, wdcclear, special_inst },
++  {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
+   {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
++  {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
+   {"mts",   INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
+   {"mfs",   INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
+   {"br",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 4cf6f077219..92c245dc0fd 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -33,8 +33,8 @@ enum microblaze_instr
+   /* 'or/and/xor' are C++ keywords.  */
+   microblaze_or, microblaze_and, microblaze_xor,
+   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+-  wic, wdc, wdcclear, wdcflush, mts, mfs, mbar, br, brd,
+-  brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
++  wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
++  brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
+   bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+   brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+-- 
+2.39.3
+
diff --git a/package/binutils/2.41/0004-opcodes-microblaze-Add-suspend-instructions.patch b/package/binutils/2.41/0004-opcodes-microblaze-Add-suspend-instructions.patch
new file mode 100644
index 0000000000..9f791bfb8a
--- /dev/null
+++ b/package/binutils/2.41/0004-opcodes-microblaze-Add-suspend-instructions.patch
@@ -0,0 +1,24 @@
+From 6487710babec2e7dcae997f79e03b9ec7d78e1c3 Mon Sep 17 00:00:00 2001
+From: Neal frager <neal.frager at amd.com>
+Date: Wed, 4 Oct 2023 16:35:44 +0100
+Subject: [PATCH] opcodes: microblaze: Add hibernate and suspend instructions
+
+---
+ opcodes/microblaze-opc.h  | 2 ++
+ 1 files changed, 2 insertions(+)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 7c70c80a27b..6b9701bb67c 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -405,6 +405,8 @@ const struct op_code_struct
+   {"clz",       INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E0, OPCODE_MASK_H34,  clz,       special_inst },
+   {"mbar",      INST_TYPE_IMM5,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB8020004, OPCODE_MASK_HN,   mbar,      special_inst },
+   {"sleep",     INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBA020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 16.  */
++  {"hibernate", INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xB9020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 8.   */
++  {"suspend",   INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 24.  */
+   {"swapb",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4,   swapb,     arithmetic_inst },
+   {"swaph",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4,   swaph,     arithmetic_inst },
+   {NULL, 0, 0, 0, 0, 0, 0, 0, 0},
+-- 
+2.39.3
diff --git a/package/binutils/2.41/0005-opcodes-microblaze-Add-address-entension-instructions.patch b/package/binutils/2.41/0005-opcodes-microblaze-Add-address-entension-instructions.patch
new file mode 100644
index 0000000000..dd92bd0d3f
--- /dev/null
+++ b/package/binutils/2.41/0005-opcodes-microblaze-Add-address-entension-instructions.patch
@@ -0,0 +1,78 @@
+From b90eb3e5b25c22ec6ee476e500aa902f77b43349 Mon Sep 17 00:00:00 2001
+From: Neal frager <neal.frager at amd.com>
+Date: Thu, 5 Oct 2023 10:59:03 +0100
+Subject: [PATCH] microblaze: Add address extension instructions
+
+  * microblaze-opcm.h (struct op_code_struct): Add address extension entries.
+  * microblaze-opc.h: Add address extension instructions.
+---
+ opcodes/microblaze-opc.h  | 9 +++++++++
+ opcodes/microblaze-opcm.h | 10 +++++-----
+ 2 files changed, 14 insertions(+), 5 deletions(-)
+
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 6b9701bb67c..7398e9e246a 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -178,8 +178,11 @@ const struct op_code_struct
+   {"wdc.ext.clear", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000466, OPCODE_MASK_H35B, wdcextclear, special_inst },
+   {"wdc.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000074, OPCODE_MASK_H34B, wdcflush, special_inst },
+   {"wdc.ext.flush", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x90000476, OPCODE_MASK_H35B, wdcextflush, special_inst },
++  {"wdc.clear.ea", INST_TYPE_R1_R2_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900000E6, OPCODE_MASK_H34B, wdcclearea, special_inst },
+   {"mts",   INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9400C000, OPCODE_MASK_H13S, mts, special_inst },
++  {"mtse",  INST_TYPE_SPECIAL_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MTS, 0x9500C000, OPCODE_MASK_H13S, mtse,special_inst },
+   {"mfs",   INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94008000, OPCODE_MASK_H23S, mfs, special_inst },
++  {"mfse",  INST_TYPE_RD_SPECIAL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_MFS, 0x94088000, OPCODE_MASK_H23S, mfse, special_inst },
+   {"br",    INST_TYPE_R2, INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98000000, OPCODE_MASK_H124, br, branch_inst },
+   {"brd",   INST_TYPE_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98100000, OPCODE_MASK_H124, brd, branch_inst },
+   {"brld",  INST_TYPE_RD_R2, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x98140000, OPCODE_MASK_H24, brld, branch_inst },
+@@ -229,18 +232,24 @@ const struct op_code_struct
+   {"bgeid", INST_TYPE_R1_IMM, INST_PC_OFFSET, DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBEA00000, OPCODE_MASK_H1, bgeid, branch_inst },
+   {"lbu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000000, OPCODE_MASK_H4, lbu, memory_load_inst },
+   {"lbur",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000200, OPCODE_MASK_H4, lbur, memory_load_inst },
++  {"lbuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC0000080, OPCODE_MASK_H4, lbuea, memory_load_inst },
+   {"lhu",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000000, OPCODE_MASK_H4, lhu, memory_load_inst },
+   {"lhur",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000200, OPCODE_MASK_H4, lhur, memory_load_inst },
++  {"lhuea", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC4000080, OPCODE_MASK_H4, lhuea, memory_load_inst },
+   {"lw",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000000, OPCODE_MASK_H4, lw, memory_load_inst },
+   {"lwr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000200, OPCODE_MASK_H4, lwr, memory_load_inst },
+   {"lwx",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000400, OPCODE_MASK_H4, lwx, memory_load_inst },
++  {"lwea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xC8000080, OPCODE_MASK_H4, lwea, memory_load_inst },
+   {"sb",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000000, OPCODE_MASK_H4, sb, memory_store_inst },
+   {"sbr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000200, OPCODE_MASK_H4, sbr, memory_store_inst },
++  {"sbea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD0000080, OPCODE_MASK_H4, sbea, memory_store_inst },
+   {"sh",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000000, OPCODE_MASK_H4, sh, memory_store_inst },
+   {"shr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000200, OPCODE_MASK_H4, shr, memory_store_inst },
++  {"shea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD4000080, OPCODE_MASK_H4, shea, memory_store_inst },
+   {"sw",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000000, OPCODE_MASK_H4, sw, memory_store_inst },
+   {"swr",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000200, OPCODE_MASK_H4, swr, memory_store_inst },
+   {"swx",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000400, OPCODE_MASK_H4, swx, memory_store_inst },
++  {"swea",  INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xD8000080, OPCODE_MASK_H4, swea, memory_store_inst },
+   {"lbui",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE0000000, OPCODE_MASK_H, lbui, memory_load_inst },
+   {"lhui",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE4000000, OPCODE_MASK_H, lhui, memory_load_inst },
+   {"lwi",   INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xE8000000, OPCODE_MASK_H, lwi, memory_load_inst },
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index 9d1df0814d9..c91b002d951 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -33,13 +33,13 @@ enum microblaze_instr
+   /* 'or/and/xor' are C++ keywords.  */
+   microblaze_or, microblaze_and, microblaze_xor,
+   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+-  wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, mts, mfs, mbar, br,
+-  brd, brld, bra, brad, brald, microblaze_brk, beq, beqd, bne, bned, blt,
+-  bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
++  wic, wdc, wdcclear, wdcextclear, wdcflush, wdcextflush, wdcclearea, mts, mtse,
++  mfs, mfse, mbar, br, brd, brld, bra, brad, brald, microblaze_brk, beq, beqd,
++  bne, bned, blt, bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni,
+   imm, rtsd, rtid, rtbd, rted, bri, brid, brlid, brai, braid, bralid,
+   brki, beqi, beqid, bnei, bneid, blti, bltid, blei, bleid, bgti,
+-  bgtid, bgei, bgeid, lbu, lbur, lhu, lhur, lw, lwr, lwx, sb, sbr, sh,
+-  shr, sw, swr, swx, lbui, lhui, lwi,
++  bgtid, bgei, bgeid, lbu, lbuea, lbur, lhu, lhuea, lhur, lw, lwea, lwr, lwx,
++  sb, sbea, sbr, sh, shea, shr, sw, swea, swr, swx, lbui, lhui, lwi,
+   sbi, shi, swi, msrset, msrclr, tuqula, mbi_fadd, frsub, mbi_fmul, mbi_fdiv,
+   fcmp_lt, fcmp_eq, fcmp_le, fcmp_gt, fcmp_ne, fcmp_ge, fcmp_un, flt,
+   /* 'fsqrt' is a glibc:math.h symbol.  */
+-- 
+2.39.3
diff --git a/package/binutils/2.41/0006-opcodes-microblaze-Add-new-bit-field-instructions.patch b/package/binutils/2.41/0006-opcodes-microblaze-Add-new-bit-field-instructions.patch
new file mode 100644
index 0000000000..12168737b0
--- /dev/null
+++ b/package/binutils/2.41/0006-opcodes-microblaze-Add-new-bit-field-instructions.patch
@@ -0,0 +1,265 @@
+From bb0d05ff74fda6b8f3f83712ebba3ea36bff1426 Mon Sep 17 00:00:00 2001
+From: Neal Frager <neal.frager at amd.com>
+Date: Fri, 13 Oct 2023 08:28:55 +0100
+Subject: [PATCH] opcodes: microblaze: Add new bit-field instructions
+
+This patches adds new bsefi and bsifi instructions.
+BSEFI- The instruction shall extract a bit field from a
+register and place it right-adjusted in the destination register.
+The other bits in the destination register shall be set to zero.
+BSIFI- The instruction shall insert a right-adjusted bit field
+from a register at another position in the destination register.
+The rest of the bits in the destination register shall be unchanged.
+
+Further documentation of these instructions can be found here:
+https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref
+
+With version 6 of the patch, no new relocation types are added as
+this was unnecessary for adding the bsefi and bsifi instructions.
+
+FIXED: Segfault caused by incorrect termination of microblaze_opcodes.
+
+Signed-off-by: nagaraju <nagaraju.mekala at amd.com>
+Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza at amd.com>
+Signed-off-by: Neal Frager <neal.frager at amd.com>
+Signed-off-by: Michael J. Eager <eager at eagercon.com>
+---
+ gas/config/tc-microblaze.c | 83 +++++++++++++++++++++++++++++++++++++-
+ opcodes/microblaze-dis.c   | 23 +++++++++++
+ opcodes/microblaze-opc.h   | 13 +++++-
+ opcodes/microblaze-opcm.h  |  6 ++-
+ 4 files changed, 121 insertions(+), 4 deletions(-)
+
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index d900a9e1d05..b510da95024 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -915,7 +915,7 @@ md_assemble (char * str)
+   unsigned reg2;
+   unsigned reg3;
+   unsigned isize;
+-  unsigned int immed = 0, temp;
++  unsigned int immed = 0, immed2 = 0, temp;
+   expressionS exp;
+   char name[20];
+ 
+@@ -1177,6 +1177,87 @@ md_assemble (char * str)
+       inst |= (immed << IMM_LOW) & IMM5_MASK;
+       break;
+ 
++    case INST_TYPE_RD_R1_IMMW_IMMS:
++      if (strcmp (op_end, ""))
++	op_end = parse_reg (op_end + 1, &reg1);  /* Get rd.  */
++      else
++	{
++	  as_fatal (_("Error in statement syntax"));
++	  reg1 = 0;
++	}
++
++      if (strcmp (op_end, ""))
++	op_end = parse_reg (op_end + 1, &reg2);  /* Get r1.  */
++      else
++	{
++	  as_fatal (_("Error in statement syntax"));
++	  reg2 = 0;
++	}
++
++      /* Check for spl registers.  */
++      if (check_spl_reg (&reg1))
++	as_fatal (_("Cannot use special register with this instruction"));
++      if (check_spl_reg (&reg2))
++	as_fatal (_("Cannot use special register with this instruction"));
++
++      /* Width immediate value.  */
++      if (strcmp (op_end, ""))
++	op_end = parse_imm (op_end + 1, &exp, MIN_IMM_WIDTH, MAX_IMM_WIDTH);
++      else
++	as_fatal (_("Error in statement syntax"));
++
++      if (exp.X_op != O_constant)
++	{
++	  as_warn (_(
++	  "Symbol used as immediate width value for bit field instruction"));
++	  immed = 1;
++	}
++      else
++	immed = exp.X_add_number;
++
++      if (opcode->instr == bsefi && immed > 31)
++	as_fatal (_("Width value must be less than 32"));
++
++      /* Shift immediate value.  */
++      if (strcmp (op_end, ""))
++	op_end = parse_imm (op_end + 1, &exp, MIN_IMM, MAX_IMM);
++      else
++	as_fatal (_("Error in statement syntax"));
++
++      if (exp.X_op != O_constant)
++	{
++	  as_warn (_(
++	  "Symbol used as immediate shift value for bit field instruction"));
++	  immed2 = 0;
++	}
++      else
++	{
++	  output = frag_more (isize);
++	  immed2 = exp.X_add_number;
++	}
++
++      if (immed2 != (immed2 % 32))
++	{
++	  as_warn (_("Shift value greater than 32. using <value %% 32>"));
++	  immed2 = immed2 % 32;
++	}
++
++      /* Check combined value.  */
++      if (immed + immed2 > 32)
++	as_fatal (_("Width value + shift value must not be greater than 32"));
++
++      inst |= (reg1 << RD_LOW) & RD_MASK;
++      inst |= (reg2 << RA_LOW) & RA_MASK;
++
++      if (opcode->instr == bsefi)
++	inst |= (immed & IMM5_MASK) << IMM_WIDTH_LOW; /* bsefi */
++      else
++	inst |= ((immed + immed2 - 1) & IMM5_MASK)
++		<< IMM_WIDTH_LOW; /* bsifi */
++
++      inst |= (immed2 << IMM_LOW) & IMM5_MASK;
++      break;
++
+     case INST_TYPE_R1_R2:
+       if (strcmp (op_end, ""))
+         op_end = parse_reg (op_end + 1, &reg1);  /* Get r1.  */
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index 12981abfea1..468797befc7 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -90,6 +90,21 @@ get_field_imm5_mbar (struct string_buf *buf, long instr)
+   return p;
+ }
+ 
++static char *
++get_field_immw (struct string_buf *buf, long instr)
++{
++  char *p = strbuf (buf);
++
++  if (instr & 0x00004000)
++    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK)
++				>> IMM_WIDTH_LOW))); /* bsefi */
++  else
++    sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >>
++				IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >>
++				IMM_LOW) + 1)); /* bsifi */
++  return p;
++}
++
+ static char *
+ get_field_rfsl (struct string_buf *buf, long instr)
+ {
+@@ -427,6 +442,14 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+ 	  /* For mbar 16 or sleep insn.  */
+ 	case INST_TYPE_NONE:
+ 	  break;
++	  /* For bit field insns.  */
++	case INST_TYPE_RD_R1_IMMW_IMMS:
++	  print_func (stream, "\t%s, %s, %s, %s",
++		      get_field_rd (&buf, inst),
++		      get_field_r1 (&buf, inst),
++		      get_field_immw (&buf, inst),
++		      get_field_imm5 (&buf, inst));
++	  break;
+ 	  /* For tuqula instruction */
+ 	case INST_TYPE_RD:
+ 	  print_func (stream, "\t%s", get_field_rd (&buf, inst));
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 7398e9e246a..811b5cbeb0f 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -59,6 +59,9 @@
+ /* For mbar.  */
+ #define INST_TYPE_IMM5 20
+ 
++/* For bsefi and bsifi */
++#define INST_TYPE_RD_R1_IMMW_IMMS  21
++
+ #define INST_TYPE_NONE 25
+ 
+ 
+@@ -90,6 +93,7 @@
+ #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits.  */
+ #define OPCODE_MASK_H3    0xFC000600 /* High 6 bits and bits 21, 22.  */
+ #define OPCODE_MASK_H32   0xFC00FC00 /* High 6 bits and bit 16-21.  */
++#define OPCODE_MASK_H32B  0xFC00C000 /* High 6 bits and bit 16, 17.  */
+ #define OPCODE_MASK_H34B  0xFC0000FF /* High 6 bits and low 8 bits.  */
+ #define OPCODE_MASK_H35B  0xFC0004FF /* High 6 bits and low 9 bits.  */
+ #define OPCODE_MASK_H34C  0xFC0007E0 /* High 6 bits and bits 21-26.  */
+@@ -102,7 +106,7 @@
+ #define DELAY_SLOT 1
+ #define NO_DELAY_SLOT 0
+ 
+-#define MAX_OPCODES 289
++#define MAX_OPCODES 291
+ 
+ const struct op_code_struct
+ {
+@@ -159,6 +163,8 @@ const struct op_code_struct
+   {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
+   {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
+   {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
++  {"bsefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
++  {"bsifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
+   {"or",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
+   {"and",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst },
+   {"xor",   INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst },
+@@ -418,7 +424,7 @@ const struct op_code_struct
+   {"suspend",   INST_TYPE_NONE,  INST_PC_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xBB020004, OPCODE_MASK_HN,   invalid_inst, special_inst }, /* translates to mbar 24.  */
+   {"swapb",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E0, OPCODE_MASK_H4,   swapb,     arithmetic_inst },
+   {"swaph",     INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x900001E2, OPCODE_MASK_H4,   swaph,     arithmetic_inst },
+-  {"", 0, 0, 0, 0, 0, 0, 0, 0},
++  {NULL, 0, 0, 0, 0, 0, 0, 0, 0},
+ };
+ 
+ /* Prefix for register names.  */
+@@ -438,5 +444,8 @@ char pvr_register_prefix[] = "rpvr";
+ #define MIN_IMM5  ((int) 0x00000000)
+ #define MAX_IMM5  ((int) 0x0000001f)
+ 
++#define MIN_IMM_WIDTH  ((int) 0x00000001)
++#define MAX_IMM_WIDTH  ((int) 0x00000020)
++
+ #endif /* MICROBLAZE_OPC */
+ 
+diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
+index c91b002d951..3c4f8948c76 100644
+--- a/opcodes/microblaze-opcm.h
++++ b/opcodes/microblaze-opcm.h
+@@ -29,7 +29,7 @@ enum microblaze_instr
+   addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul,
+   mulh, mulhu, mulhsu, swapb, swaph,
+   idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput,
+-  ncget, ncput, muli, bslli, bsrai, bsrli, mului,
++  ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului,
+   /* 'or/and/xor' are C++ keywords.  */
+   microblaze_or, microblaze_and, microblaze_xor,
+   andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16,
+@@ -130,6 +130,7 @@ enum microblaze_instr_type
+ #define RB_LOW  11 /* Low bit for RB.  */
+ #define IMM_LOW  0 /* Low bit for immediate.  */
+ #define IMM_MBAR 21 /* low bit for mbar instruction.  */
++#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */
+ 
+ #define RD_MASK 0x03E00000
+ #define RA_MASK 0x001F0000
+@@ -142,6 +143,9 @@ enum microblaze_instr_type
+ /* Imm mask for mbar.  */
+ #define IMM5_MBAR_MASK 0x03E00000
+ 
++/* Imm mask for extract/insert width. */
++#define IMM5_WIDTH_MASK 0x000007C0
++
+ /* FSL imm mask for get, put instructions.  */
+ #define  RFSL_MASK 0x000000F
+ 
+-- 
+2.39.3
diff --git a/package/binutils/2.41/0007-bfd-microblaze-Add-32_NONE-reloc-type.patch b/package/binutils/2.41/0007-bfd-microblaze-Add-32_NONE-reloc-type.patch
new file mode 100644
index 0000000000..4d0b3d097e
--- /dev/null
+++ b/package/binutils/2.41/0007-bfd-microblaze-Add-32_NONE-reloc-type.patch
@@ -0,0 +1,180 @@
+From aea4f3261d558017e9168f85dd200a0fc975e65d Mon Sep 17 00:00:00 2001
+From: Neal Frager <neal.frager at amd.com>
+Date: Mon, 16 Oct 2023 18:27:05 +0100
+Subject: [PATCH] bfd: microblaze: Add 32_NONE reloc type
+
+This patch adds the R_MICROBLAZE_32_NONE relocation type.
+This is a 32-bit reloc that stores the 32-bit pc relative
+value in two words (with an imm instruction).
+
+Signed-off-by: Neal Frager <neal.frager at amd.com>
+---
+ bfd/bfd-in2.h              |  5 +++++
+ bfd/elf32-microblaze.c     | 25 +++++++++++++++++++++++--
+ bfd/libbfd.h               |  1 +
+ bfd/reloc.c                |  6 ++++++
+ binutils/readelf.c         |  4 ++++
+ gas/config/tc-microblaze.c |  3 +++
+ include/elf/microblaze.h   |  1 +
+ 7 files changed, 43 insertions(+), 2 deletions(-)
+
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index c1fe48bb2f1..fb0ead46aba 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -6463,6 +6463,11 @@ value relative to the read-write small data area anchor  */
+ expressions of the form "Symbol Op Symbol"  */
+   BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM,
+ 
++/* This is a 32 bit reloc that stores the 32 bit pc relative
++value in two words (with an imm instruction).No relocation is 
++done here - only used for relaxing  */
++  BFD_RELOC_MICROBLAZE_32_NONE,
++
+ /* This is a 64 bit reloc that stores the 32 bit pc relative
+ value in two words (with an imm instruction).  No relocation is
+ done here - only used for relaxing  */
+diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
+index a7e81c70fc8..c10278cde31 100644
+--- a/bfd/elf32-microblaze.c
++++ b/bfd/elf32-microblaze.c
+@@ -174,6 +174,21 @@ static reloc_howto_type microblaze_elf_howto_raw[] =
+ 	  0x0000ffff,		/* Dest Mask.  */
+ 	  false),		/* PC relative offset?  */
+ 
++   /* This reloc does nothing.	Used for relaxation.  */
++   HOWTO (R_MICROBLAZE_32_NONE,	/* Type.  */
++	0,			/* Rightshift.  */
++	2,			/* Size (0 = byte, 1 = short, 2 = long).  */
++	32,			/* Bitsize.  */
++	true,			/* PC_relative.  */
++	0,			/* Bitpos.  */
++	complain_overflow_bitfield, /* Complain on overflow.  */
++	NULL,			/* Special Function.  */
++	"R_MICROBLAZE_32_NONE", /* Name.  */
++	false,			/* Partial Inplace.  */
++	0,			/* Source Mask.  */
++	0,			/* Dest Mask.  */
++	false),		/* PC relative offset?  */
++
+    /* This reloc does nothing.	Used for relaxation.  */
+    HOWTO (R_MICROBLAZE_64_NONE,	/* Type.  */
+ 	  0,			/* Rightshift.  */
+@@ -560,6 +575,9 @@ microblaze_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED,
+     case BFD_RELOC_NONE:
+       microblaze_reloc = R_MICROBLAZE_NONE;
+       break;
++    case BFD_RELOC_MICROBLAZE_32_NONE:
++      microblaze_reloc = R_MICROBLAZE_32_NONE;
++      break;
+     case BFD_RELOC_MICROBLAZE_64_NONE:
+       microblaze_reloc = R_MICROBLAZE_64_NONE;
+       break;
+@@ -1954,6 +1972,7 @@ microblaze_elf_relax_section (bfd *abfd,
+ 		}
+ 	      break;
+ 	    case R_MICROBLAZE_NONE:
++	    case R_MICROBLAZE_32_NONE:
+ 	      {
+ 		/* This was a PC-relative instruction that was
+ 		   completely resolved.  */
+@@ -2009,7 +2028,9 @@ microblaze_elf_relax_section (bfd *abfd,
+ 	  irelscanend = irelocs + o->reloc_count;
+ 	  for (irelscan = irelocs; irelscan < irelscanend; irelscan++)
+ 	    {
+-	      if (ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32)
++	      if ((ELF32_R_TYPE (irelscan->r_info) == (int) R_MICROBLAZE_32) ||
++		  (ELF32_R_TYPE (irelscan->r_info) ==
++		  (int) R_MICROBLAZE_32_NONE))
+ 		{
+ 		  isym = isymbuf + ELF32_R_SYM (irelscan->r_info);
+ 
+@@ -2068,7 +2089,7 @@ microblaze_elf_relax_section (bfd *abfd,
+ 			      elf_section_data (o)->this_hdr.contents = ocontents;
+ 			    }
+ 			}
+-		      irelscan->r_addend -= calc_fixup (irel->r_addend
++		      irelscan->r_addend -= calc_fixup (irelscan->r_addend
+ 							+ isym->st_value,
+ 							0,
+ 							sec);
+diff --git a/bfd/libbfd.h b/bfd/libbfd.h
+index d5f42f22c08..d729dc48e7c 100644
+--- a/bfd/libbfd.h
++++ b/bfd/libbfd.h
+@@ -3010,6 +3010,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
+   "BFD_RELOC_MICROBLAZE_32_ROSDA",
+   "BFD_RELOC_MICROBLAZE_32_RWSDA",
+   "BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM",
++  "BFD_RELOC_MICROBLAZE_32_NONE",
+   "BFD_RELOC_MICROBLAZE_64_NONE",
+   "BFD_RELOC_MICROBLAZE_64_GOTPC",
+   "BFD_RELOC_MICROBLAZE_64_GOT",
+diff --git a/bfd/reloc.c b/bfd/reloc.c
+index 2ac883d0eac..3ea2afc0d4e 100644
+--- a/bfd/reloc.c
++++ b/bfd/reloc.c
+@@ -6694,6 +6694,12 @@ ENUM
+ ENUMDOC
+   This is a 32 bit reloc for the microblaze to handle
+   expressions of the form "Symbol Op Symbol"
++ENUM
++  BFD_RELOC_MICROBLAZE_32_NONE
++ENUMDOC
++  This is a 32 bit reloc that stores the 32 bit pc relative
++  value in two words (with an imm instruction).  No relocation is
++  done here - only used for relaxing
+ ENUM
+   BFD_RELOC_MICROBLAZE_64_NONE
+ ENUMDOC
+diff --git a/binutils/readelf.c b/binutils/readelf.c
+index c9b6210e229..17fd7066b83 100644
+--- a/binutils/readelf.c
++++ b/binutils/readelf.c
+@@ -15279,6 +15279,10 @@ is_8bit_abs_reloc (Filedata * filedata, unsigned int reloc_type)
+       return reloc_type == 54; /* R_RISCV_SET8.  */
+     case EM_Z80:
+       return reloc_type == 1;  /* R_Z80_8.  */
++    case EM_MICROBLAZE:
++      return reloc_type == 33 /* R_MICROBLAZE_32_NONE.  */
++		|| reloc_type == 0 /* R_MICROBLAZE_NONE.  */
++		|| reloc_type == 9; /* R_MICROBLAZE_64_NONE.  */
+     default:
+       return false;
+     }
+diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
+index b510da95024..604cc935da9 100644
+--- a/gas/config/tc-microblaze.c
++++ b/gas/config/tc-microblaze.c
+@@ -2290,6 +2290,8 @@ md_apply_fix (fixS *   fixP,
+ 	 moves code around due to relaxing.  */
+       if (fixP->fx_r_type == BFD_RELOC_64_PCREL)
+ 	fixP->fx_r_type = BFD_RELOC_MICROBLAZE_64_NONE;
++      else if (fixP->fx_r_type == BFD_RELOC_32)
++	fixP->fx_r_type = BFD_RELOC_MICROBLAZE_32_NONE;
+       else
+ 	fixP->fx_r_type = BFD_RELOC_NONE;
+       fixP->fx_addsy = section_symbol (absolute_section);
+@@ -2513,6 +2515,7 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED, fixS * fixp)
+   switch (fixp->fx_r_type)
+     {
+     case BFD_RELOC_NONE:
++    case BFD_RELOC_MICROBLAZE_32_NONE:
+     case BFD_RELOC_MICROBLAZE_64_NONE:
+     case BFD_RELOC_32:
+     case BFD_RELOC_MICROBLAZE_32_LO:
+diff --git a/include/elf/microblaze.h b/include/elf/microblaze.h
+index fecdd7e4831..164b36d0978 100644
+--- a/include/elf/microblaze.h
++++ b/include/elf/microblaze.h
+@@ -61,6 +61,7 @@ START_RELOC_NUMBERS (elf_microblaze_reloc_type)
+   RELOC_NUMBER (R_MICROBLAZE_TEXTPCREL_64, 30)  /* PC-relative TEXT offset.  */
+   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_64, 31)    /* TEXT Entry offset 64-bit.  */
+   RELOC_NUMBER (R_MICROBLAZE_TEXTREL_32_LO, 32) /* TEXT Entry offset 32-bit.  */
++  RELOC_NUMBER (R_MICROBLAZE_32_NONE, 33)
+ END_RELOC_NUMBERS (R_MICROBLAZE_max)
+ 
+ /* Global base address names.  */
+-- 
+2.25.1
+
diff --git a/package/binutils/2.41/0008-opcodes-microblaze-Fix-bit-masking-bug.patch b/package/binutils/2.41/0008-opcodes-microblaze-Fix-bit-masking-bug.patch
new file mode 100644
index 0000000000..7101922848
--- /dev/null
+++ b/package/binutils/2.41/0008-opcodes-microblaze-Fix-bit-masking-bug.patch
@@ -0,0 +1,80 @@
+From b9c6c00c1b399e52a1255a541c30a44d2d11cfd1 Mon Sep 17 00:00:00 2001
+From: Neal Frager <neal.frager at amd.com>
+Date: Thu, 19 Oct 2023 12:36:09 +0100
+Subject: [PATCH] opcodes: microblaze: Fix bit masking bug
+
+There is currently a bug in the bit masking for the barrel shift
+instructions because the bit mask is not including all of the
+register bits which must be zero.  With this patch, the disassembler
+can be sure that the 32-bit value is indeed a barrel shift instruction
+and not a data value in memory.
+
+This fix can be verified by assembling and disassembling the following:
+
+	.text
+	.long 0x65005f5f
+
+With this patch, the bug is fixed, and the objdump will know that
+0x65005f5f is not a barrel shift instruction.
+
+Signed-off-by: Neal Frager <neal.frager at amd.com>
+---
+ opcodes/microblaze-dis.c               |  4 ++--
+ opcodes/microblaze-opc.h               | 11 +++++++----
+ 3 files changed, 9 insertions(+), 6 deletions(-)
+
+diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
+index 468797befc7..0b5262255fb 100644
+--- a/opcodes/microblaze-dis.c
++++ b/opcodes/microblaze-dis.c
+@@ -35,7 +35,7 @@
+ #define get_int_field_imm(instr)   ((instr & IMM_MASK) >> IMM_LOW)
+ #define get_int_field_r1(instr)    ((instr & RA_MASK) >> RA_LOW)
+ 
+-#define NUM_STRBUFS 3
++#define NUM_STRBUFS 4
+ #define STRBUF_SIZE 25
+ 
+ struct string_buf
+@@ -279,7 +279,7 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info)
+   prev_insn_vma = curr_insn_vma;
+ 
+   if (op->name == NULL)
+-    print_func (stream, ".short 0x%04x", (unsigned int) inst);
++    print_func (stream, ".long 0x%04x", (unsigned int) inst);
+   else
+     {
+       print_func (stream, "%s", op->name);
+diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h
+index 811b5cbeb0f..b9045f67969 100644
+--- a/opcodes/microblaze-opc.h
++++ b/opcodes/microblaze-opc.h
+@@ -92,8 +92,11 @@
+ #define OPCODE_MASK_H124  0xFFFF07FF /* High 16, and low 11 bits.  */
+ #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits.  */
+ #define OPCODE_MASK_H3    0xFC000600 /* High 6 bits and bits 21, 22.  */
++#define OPCODE_MASK_H3B   0xFC00F9E0 /* High 6 bits and bits 16:20 and
++					bits 23:26. */
+ #define OPCODE_MASK_H32   0xFC00FC00 /* High 6 bits and bit 16-21.  */
+-#define OPCODE_MASK_H32B  0xFC00C000 /* High 6 bits and bit 16, 17.  */
++#define OPCODE_MASK_H32B  0xFC00F820 /* High 6 bits and bits 16:20 and
++					bit 26 */
+ #define OPCODE_MASK_H34B  0xFC0000FF /* High 6 bits and low 8 bits.  */
+ #define OPCODE_MASK_H35B  0xFC0004FF /* High 6 bits and low 9 bits.  */
+ #define OPCODE_MASK_H34C  0xFC0007E0 /* High 6 bits and bits 21-26.  */
+@@ -160,9 +163,9 @@ const struct op_code_struct
+   {"ncget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C006000, OPCODE_MASK_H32, ncget, anyware_inst },
+   {"ncput", INST_TYPE_R1_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C00E000, OPCODE_MASK_H32, ncput, anyware_inst },
+   {"muli",  INST_TYPE_RD_R1_IMM, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x60000000, OPCODE_MASK_H, muli, mult_inst },
+-  {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst },
+-  {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst },
+-  {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst },
++  {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3B, bslli, barrel_shift_inst },
++  {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3B, bsrai, barrel_shift_inst },
++  {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3B, bsrli, barrel_shift_inst },
+   {"bsefi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst },
+   {"bsifi", INST_TYPE_RD_R1_IMMW_IMMS, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst },
+   {"or",    INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst },
+-- 
+2.25.1
+
-- 
2.25.1




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