[Buildroot] [PATCH v1 1/2] configs/zynqmp_zcu102_defconfig: bump to xilinx-v2023.1
Neal Frager
neal.frager at amd.com
Tue May 30 07:15:57 UTC 2023
This patch bumps the zynqmp_zcu102_defconfig to xilinx-v2023.1 which includes
the following updates:
- Linux v6.1.5
- U-Boot v2023.01
- ATF v2.8
- PMUFW xilinx_v2023.1
- Updated pm_cfg_obj.c from Vitis v2023.1
Signed-off-by: Neal Frager <neal.frager at amd.com>
---
board/zynqmp/zcu102/pm_cfg_obj.c | 51 ++++----------------------------
configs/zynqmp_zcu102_defconfig | 11 +++----
2 files changed, 11 insertions(+), 51 deletions(-)
diff --git a/board/zynqmp/zcu102/pm_cfg_obj.c b/board/zynqmp/zcu102/pm_cfg_obj.c
index 68557c4cb4..04bfb16e35 100644
--- a/board/zynqmp/zcu102/pm_cfg_obj.c
+++ b/board/zynqmp/zcu102/pm_cfg_obj.c
@@ -30,6 +30,9 @@
#define SUSPEND_TIMEOUT 0xFFFFFFFFU
+#define PM_CONFIG_OBJECT_TYPE_BASE 0x1U
+
+
#define PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK 0x00000001
#define PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK 0x00000100
#define PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK 0x00000200
@@ -51,7 +54,7 @@ __root const u32 XPm_ConfigObject[] =
/* HEADER */
2, /* Number of remaining words in the header */
8, /* Number of sections included in config object */
- 1U, /* Type of config object as base */
+ PM_CONFIG_OBJECT_TYPE_BASE, /* Type of config object as base */
/**********************************************************************/
/* MASTER SECTION */
PM_CONFIG_MASTER_SECTION_ID, /* Master SectionID */
@@ -81,7 +84,7 @@ __root const u32 XPm_ConfigObject[] =
PM_CONFIG_SLAVE_SECTION_ID, /* Section ID */
- 49, /* Number of slaves */
+ 38, /* Number of slaves */
NODE_OCM_BANK_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
@@ -131,10 +134,6 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
- NODE_USB_1,
- PM_SLAVE_FLAG_IS_SHAREABLE,
- 0U, /* IPI Mask */
-
NODE_TTC_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@@ -155,18 +154,6 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
- NODE_ETH_0,
- PM_SLAVE_FLAG_IS_SHAREABLE,
- 0U, /* IPI Mask */
-
- NODE_ETH_1,
- PM_SLAVE_FLAG_IS_SHAREABLE,
- 0U, /* IPI Mask */
-
- NODE_ETH_2,
- PM_SLAVE_FLAG_IS_SHAREABLE,
- 0U, /* IPI Mask */
-
NODE_ETH_3,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@@ -179,14 +166,6 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
- NODE_SPI_0,
- PM_SLAVE_FLAG_IS_SHAREABLE,
- 0U, /* IPI Mask */
-
- NODE_SPI_1,
- PM_SLAVE_FLAG_IS_SHAREABLE,
- 0U, /* IPI Mask */
-
NODE_I2C_0,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@@ -195,10 +174,6 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
- NODE_SD_0,
- PM_SLAVE_FLAG_IS_SHAREABLE,
- 0U, /* IPI Mask */
-
NODE_SD_1,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@@ -215,10 +190,6 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
- NODE_NAND,
- PM_SLAVE_FLAG_IS_SHAREABLE,
- 0U, /* IPI Mask */
-
NODE_QSPI,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@@ -227,10 +198,6 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
- NODE_CAN_0,
- PM_SLAVE_FLAG_IS_SHAREABLE,
- 0U, /* IPI Mask */
-
NODE_CAN_1,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
@@ -263,18 +230,10 @@ __root const u32 XPm_ConfigObject[] =
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
- NODE_PCAP,
- PM_SLAVE_FLAG_IS_SHAREABLE,
- 0U, /* IPI Mask */
-
NODE_RTC,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
- NODE_VCU,
- PM_SLAVE_FLAG_IS_SHAREABLE,
- 0U, /* IPI Mask */
-
NODE_PL,
PM_SLAVE_FLAG_IS_SHAREABLE,
PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK | PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK, /* IPI Mask */
diff --git a/configs/zynqmp_zcu102_defconfig b/configs/zynqmp_zcu102_defconfig
index 00b33261b6..da62be8203 100644
--- a/configs/zynqmp_zcu102_defconfig
+++ b/configs/zynqmp_zcu102_defconfig
@@ -1,11 +1,11 @@
BR2_aarch64=y
-BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_15=y
+BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_6_1=y
BR2_ROOTFS_POST_BUILD_SCRIPT="board/zynqmp/post-build.sh"
BR2_ROOTFS_POST_IMAGE_SCRIPT="board/zynqmp/post-image.sh"
BR2_ROOTFS_POST_SCRIPT_ARGS="ttyPS0,115200 mmcblk0p2"
BR2_LINUX_KERNEL=y
BR2_LINUX_KERNEL_CUSTOM_TARBALL=y
-BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,linux-xlnx,xlnx_rebase_v5.15_LTS_2022.2)/xlnx_rebase_v5.15_LTS_2022.2.tar.gz"
+BR2_LINUX_KERNEL_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,linux-xlnx,xlnx_rebase_v6.1_LTS_2023.1)/xlnx_rebase_v6.1_LTS_2023.1.tar.gz"
BR2_LINUX_KERNEL_DEFCONFIG="xilinx_zynqmp"
BR2_LINUX_KERNEL_DTS_SUPPORT=y
BR2_LINUX_KERNEL_INTREE_DTS_NAME="xilinx/zynqmp-zcu102-rev1.0"
@@ -15,21 +15,22 @@ BR2_TARGET_ROOTFS_EXT2_4=y
# BR2_TARGET_ROOTFS_TAR is not set
BR2_TARGET_ARM_TRUSTED_FIRMWARE=y
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL=y
-BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,arm-trusted-firmware,xlnx_rebase_v2.6_2022.2)/xlnx_rebase_v2.6_2022.2.tar.gz"
+BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,arm-trusted-firmware,xlnx_rebase_v2.8_2023.1)/xlnx_rebase_v2.8_2023.1.tar.gz"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_PLATFORM="zynqmp"
BR2_TARGET_ARM_TRUSTED_FIRMWARE_BL31_UBOOT=y
BR2_TARGET_UBOOT=y
BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y
BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
-BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,u-boot-xlnx,xlnx_rebase_v2022.01_2022.2)/xlnx_rebase_v2022.01_2022.2.tar.gz"
+BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="$(call github,Xilinx,u-boot-xlnx,xlnx_rebase_v2023.01_2023.1)/xlnx_rebase_v2023.01_2023.1.tar.gz"
BR2_TARGET_UBOOT_BOARD_DEFCONFIG="xilinx_zynqmp_virt"
BR2_TARGET_UBOOT_CUSTOM_MAKEOPTS="DEVICE_TREE=zynqmp-zcu102-rev1.0"
BR2_TARGET_UBOOT_NEEDS_DTC=y
BR2_TARGET_UBOOT_NEEDS_OPENSSL=y
+BR2_TARGET_UBOOT_NEEDS_GNUTLS=y
BR2_TARGET_UBOOT_SPL=y
BR2_TARGET_UBOOT_SPL_NAME="spl/boot.bin"
BR2_TARGET_UBOOT_ZYNQMP=y
-BR2_TARGET_UBOOT_ZYNQMP_PMUFW="https://github.com/Xilinx/ubuntu-firmware/raw/2022.2_br_1/zcu102/zcu102_pmufw.elf"
+BR2_TARGET_UBOOT_ZYNQMP_PMUFW="https://github.com/Xilinx/soc-prebuilt-firmware/raw/xilinx_v2023.1/zcu102-zynqmp/pmufw.elf"
BR2_TARGET_UBOOT_ZYNQMP_PM_CFG="board/zynqmp/zcu102/pm_cfg_obj.c"
BR2_TARGET_UBOOT_FORMAT_ITB=y
BR2_TARGET_UBOOT_NEEDS_ATF_BL31=y
--
2.17.1
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