[Buildroot] [PATCH v3 1/3] arch/Config.in.riscv: update instruction set ext

[Yann E. MORIN]

Jamie, All,

On 2023-08-18 11:42 +0100, Jamie Gibbons via buildroot spake thusly:
> Allow a RISC-V G core to support C and V. Copy custom RVC and RVV
> instructions from RISC-V custom core to RISC-V general core.

After discussing with Thomas on IRC, I applied the patch, but using the
construct I proposed in my review of v2.

This diverges substantially from what your patch does, but I think it is
a bit nicer, if at lesat because the user has direct feedback of what
sets generic implies (and that yes, we mean the same thing as the riscv
spec says).

Applied to next, thanks.

Regards,
Yann E. MORIN.

> Signed-off-by: Jamie Gibbons <jamie.gibbons at microchip.com>
> ---
> 
> v1 -> v2 changes:
> - copied RVC and RVV kconfigs to both riscv_g and riscv_custom
> 
> v2 -> v3 changes:
> - removed duplicate menu options
> 
>  arch/Config.in.riscv | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv
> index 3dfbb4165f..df8499c7a0 100644
> --- a/arch/Config.in.riscv
> +++ b/arch/Config.in.riscv
> @@ -41,10 +41,10 @@ config BR2_riscv_custom
>  
>  endchoice
>  
> -if BR2_riscv_custom
> -
>  comment "Instruction Set Extensions"
>  
> +if BR2_riscv_custom
> +
>  config BR2_RISCV_ISA_CUSTOM_RVM
>  	bool "Integer Multiplication and Division (M)"
>  	select BR2_RISCV_ISA_RVM
> @@ -62,6 +62,8 @@ config BR2_RISCV_ISA_CUSTOM_RVD
>  	depends on BR2_RISCV_ISA_RVF
>  	select BR2_RISCV_ISA_RVD
>  
> +endif
> +
>  config BR2_RISCV_ISA_CUSTOM_RVC
>  	bool "Compressed Instructions (C)"
>  	select BR2_RISCV_ISA_RVC
> @@ -71,8 +73,6 @@ config BR2_RISCV_ISA_CUSTOM_RVV
>  	select BR2_RISCV_ISA_RVV
>  	select BR2_ARCH_NEEDS_GCC_AT_LEAST_12
>  
> -endif
> -
>  choice
>  	prompt "Target Architecture Size"
>  	default BR2_RISCV_64
> -- 
> 2.34.1
> 
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