[Buildroot] [PATCH v2 1/3] arch/Config.in.riscv: update instruction set ext

[Thomas Petazzoni]

On Wed, 16 Aug 2023 17:04:42 +0200
"Yann E. MORIN" <yann.morin.1998 at free.fr> wrote:

> Basically, I think what Thomas expects is something like:
> 
>     diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv
>     index 3dfbb4165f..997f7a631d 100644
>     --- a/arch/Config.in.riscv
>     +++ b/arch/Config.in.riscv
>     @@ -1,26 +1,5 @@
>      # RISC-V CPU ISA extensions.
>      
>     -config BR2_RISCV_ISA_RVI
>     -    bool
>     -
>     -config BR2_RISCV_ISA_RVM
>     -    bool
>     -
>     -config BR2_RISCV_ISA_RVA
>     -    bool
>     -
>     -config BR2_RISCV_ISA_RVF
>     -    bool
>     -
>     -config BR2_RISCV_ISA_RVD
>     -    bool
>     -
>     -config BR2_RISCV_ISA_RVC
>     -    bool
>     -
>     -config BR2_RISCV_ISA_RVV
>     -    bool
>     -
>      choice
>          prompt "Target Architecture Variant"
>          default BR2_riscv_g
>     @@ -41,38 +20,28 @@ config BR2_riscv_custom
> 
>      endchoice
> 
>     -if BR2_riscv_custom
>     -
>      comment "Instruction Set Extensions"
> 
>     -config BR2_RISCV_ISA_CUSTOM_RVM
>     +config BR2_RISCV_ISA_RVM
>          bool "Integer Multiplication and Division (M)"
>     -    select BR2_RISCV_ISA_RVM
> 
>     -config BR2_RISCV_ISA_CUSTOM_RVA
>     +config BR2_RISCV_ISA_RVA
>          bool "Atomic Instructions (A)"
>     -    select BR2_RISCV_ISA_RVA
> 
>     -config BR2_RISCV_ISA_CUSTOM_RVF
>     +config BR2_RISCV_ISA_RVF
>          bool "Single-precision Floating-point (F)"
>     -    select BR2_RISCV_ISA_RVF
> 
>     -config BR2_RISCV_ISA_CUSTOM_RVD
>     +config BR2_RISCV_ISA_RVD
>          bool "Double-precision Floating-point (D)"
>          depends on BR2_RISCV_ISA_RVF
>     -    select BR2_RISCV_ISA_RVD
> 
>     -config BR2_RISCV_ISA_CUSTOM_RVC
>     +config BR2_RISCV_ISA_RVC
>          bool "Compressed Instructions (C)"
>     -    select BR2_RISCV_ISA_RVC
> 
>     -config BR2_RISCV_ISA_CUSTOM_RVV
>     +config BR2_RISCV_ISA_RVV
>          bool "Vector Instructions (V)"
>     -    select BR2_RISCV_ISA_RVV
>          select BR2_ARCH_NEEDS_GCC_AT_LEAST_12
> 
>     -endif
>     -
>      choice
>          prompt "Target Architecture Size"
>          default BR2_RISCV_64
> 
> Thomas?

Not quite, because we want the IMAFD options to remain under the
"custom" option.

Essentially what happens today is:

 - RISC-V G implies IMAFD, but there is no way to say I have G + C + V

 - RISC-V custom allows any combination of IMAFDCV

What we want is:

 - RISC-V G implies IMAFD, but also allows to select C and V

 - RISC-V custom allows any combination of IMAFDCV

So something like this:

diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv
index 3dfbb4165f..df8499c7a0 100644
--- a/arch/Config.in.riscv
+++ b/arch/Config.in.riscv
@@ -41,10 +41,10 @@ config BR2_riscv_custom
 
 endchoice
 
-if BR2_riscv_custom
-
 comment "Instruction Set Extensions"
 
+if BR2_riscv_custom
+
 config BR2_RISCV_ISA_CUSTOM_RVM
 	bool "Integer Multiplication and Division (M)"
 	select BR2_RISCV_ISA_RVM
@@ -62,6 +62,8 @@ config BR2_RISCV_ISA_CUSTOM_RVD
 	depends on BR2_RISCV_ISA_RVF
 	select BR2_RISCV_ISA_RVD
 
+endif
+
 config BR2_RISCV_ISA_CUSTOM_RVC
 	bool "Compressed Instructions (C)"
 	select BR2_RISCV_ISA_RVC
@@ -71,8 +73,6 @@ config BR2_RISCV_ISA_CUSTOM_RVV
 	select BR2_RISCV_ISA_RVV
 	select BR2_ARCH_NEEDS_GCC_AT_LEAST_12
 
-endif
-
 choice
 	prompt "Target Architecture Size"
 	default BR2_RISCV_64

Note that indeed the blind options BR2_RISCV_ISA_RVC and
BR2_RISCV_ISA_RVV are no longer very useful, but I guess I would keep
them anyway to keep the symmetry with BR2_RISCV_ISA_RV{I,M,A,F,D} blind
options.

Thoughts?

Thomas
-- 
Thomas Petazzoni, co-owner and CEO, Bootlin
Embedded Linux and Kernel engineering and training
https://bootlin.com